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introduce compiler switches to simply chose between those processor types
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define common names for those register names being different
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read the vendor's migration directives in document "tiny26to861.pdf"
considerations
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pay attention to the clock system, since there are advanced features for the ATtiny861
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you select clock source via fuse bits CKSEL3:0
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the ATtiny861 is shipped with internal RC-oscillator enabled @ 8MHz
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you select clock prescaling via CLKPS3:0 bits of the CLKPR (clock prescale register), possible @ runtime
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factory default of system clock prescaler (CLKPR) is 8, so the source clock value is 1MHz for all subsystems
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the resulting system clock is a combination of paragraphs 4.1 through 4.4
controller initialization
ACSRA - Analog Comparator Control and Status Register A
ACD | ACBG | ACO | ACI | ACIE | ACME | ACIS1 | ACIS0 |
1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
set ACD bit to '1' to disable analog comparator
Port A init is done by LCD routines (leave default)
DDRB - Port B Data Direction Register
DDB7 | DDB6 | DDB5 | DDB4 | DDB3 | DDB2 | DDB1 | DDB0 |
0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 |
configure PB3 & PB4 as output
PORTB - Port B Data Register
PORTB7 | PORTB6 | PORTB5 | PORTB4 | PORTB3 | PORTB2 | PORTB1 | PORTB0 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
setting up timer/counter0 to 100ms period, normal 8 bit mode
the theory
timer clock = system clock / clock prescaler / timer prescaler
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where system clock = 8MHz (factory default), clock prescaler = 8 (factory default), timer prescaler = 1024
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this results in a timer clock of 1,024ms and a timer period of 100,352ms
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when using a timer reload value of 98 the error hereby is 0,352ms which is 12,672s per hour or 30,83 hours per year
registers and bits affected
CLKPR <- Clock Prescale Register (leave default)
CLKPCE | - | - | - | CLKPS3 | CLKPS2 | CLKPS1 | CLKPS0 |
0 | - | - | - | 0 | 0 | 1 | 1 |
CLKPCE <- Clock Prescaler Change Enable
factory default is CKDIV8 Fuse programmed -> CLKPS0 & CLKPS1 = 1
TCNT0L <- Timer/Counter0 Register Low Byte
this is where we store our counter value
TCCR0A <- Timer/Counter0 Control Register A (leave default)
TCW0 | ICEN0 | ICNC0 | ICES0 | ACIC0 | - | - | CTC0 |
0 | 0 | 0 | 0 | 0 | - | - | 0 |
mode selection:
ICEN0 | TCW0 | CTC0 |
input capture enable | timer counter width | wave form generation |
TCCR0B <- Timer/Counter0 Control Register B
- | - | - | TSM | PSR0 | CS02 | CS01 | CS00 |
- | - | - | 0 | 0 | 1 | 0 | 1 |
clock selection:
CS02:CS00, we need a clkio division of 1024
TIMSK <- Timer/Counter0/1 Interrupt Mask Register
OCIE1D | OCIE1A | OCIE1B | OCIE0A | OCIE0B | TOIE1 | TOIE0 | TICIE0 |
0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 |
enable timer interrupt on overflow:
TOIE0 <- Timer/Counter0 Overflow Interrupt Enable
ADC
ADMUX - ADC Multiplexer Selection Register (leave default)
REFS1 | REFS0 | ADLAR | MUX4 | MUX3 | MUX2 | MUX1 | MUX0 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
using AVCC as ref voltage through low pass filter
ADCSRA - ADC Control and Status Register A
ADEN | ADSC | ADATE | ADIF | ADIE | ADPS2 | ADPS1 | ADPS0 |
1 | 1 | 0 | 0 | 1 | 0 | 1 | 1 |
that means:
ADEN | ADSC | ADIE | ADPS1 |
enable ADC | start conversion immediately to consumpt the initial 25 ADC cycles | enable ADC interrupt | prescaler source clock / 8 = 125KHz |
ADCSRB - ADC Control and Status Register B (leave default)
BIN | GSEL | - | REFS2 | MUX5 | ADTS2 | ADTS1 | ADTS0 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Controlling algorithm
strategy
there are two possible (imaginable) strategies for temperature controlling
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controlling the forerun dependent on the outer temperature (heating curve)
disadvantages are
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the non-considered insulation capability of the house
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beside the sensor characteristics the heating curve must be defined and evaluated
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phantom inner temperature changes are poorly considered
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require a forerun sensor
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controlling the inner temperature individually, dependent on nominal
disadvantages are
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non-trivial recognition of phantom inner temperature changes
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require an inner temp sensor
principle
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inner temperature measurement in living room (one sensor)
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outer temperature measurement 7cm in the wall facing to north (from outside)
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if the inner temperature gets lowered the mixer has to be positioned to get warmer water into the floor heater system and vice versa
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at the time there is no recognition when the mixer motor reaches one of its end positions
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the mixer is controlled continuously depending on a t.b.d temperature difference (nominal - inner)
problems
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there is also a temperature sensor for the forerun, but I have no idea, what to do with that value this time
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any disturbance which lowers the inner temperature can be balanced more or less fast (depending on the grade of influx and possibly depending on the forerun. But a disturbance which raises the inner temp is usually a consecution of a higher outer temperature. Heating the oven or a meeting of many people are exceptions which should be considered very slightly. Otherwise the heating system would be driven down by too far and all other rooms would become very cold
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in general a difference of the inner temperature depends on natural changes of the outer temperature. Any other disturbance must be handled exceptional. We likely can recognize such exceptions by continuously tracking the inner and outer temp gradients and then react very smoothly against the system
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it has t.b.d (evaluated)
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in which intervals (distance and length) the
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mixer motor should be driven
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the temperatures shall be aquired (controlling cycle)
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what's a significant change of the outer temperature?
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on which difference of the inner temp to the nominal the mixer has to be moved
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what's the benefit of tracking the forerun temp
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the characteristic of the original sensors has to be identified, which in turn is non-linear. We'd like to get the temperature quantity out of that data. A colleague of Woifi could help us out here
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lowering the whole system over night is not planned this time
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what to do if
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the inner temp has become higher than the nominal (e.g. wooden oven fired) while the outer temp goes down and down
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the inner temp does not follow the counteraction to the outer temp in a specific interval
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a change of the outer temp takes hours to affect the inner temp
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do controlling by inner temp in very little steps to
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compensate outer temp deviations fast but stressless
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avoid overshooting of the inner temp
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do controlling of the forerun if the inner temp has become higher than the nominal (due to disturbance)
here we can define some considerations
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time between cycle intervals: 5min
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mixer engine controlling time: 1s
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temperature capture interval: 5s
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total amount of temperature values during cycle intervals: 300s/5s = 60
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setting up timer intervals on uC:
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system clock fs = 8MHz
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fs prescaler ps = 2
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timer0 prescaler t0ps = 1024
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timer0 frequency f0 = fs/ps/t0ps = 3906.25Hz
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timer0 overflow freq f0ov=f0/255 = 15.318627451Hz
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timer0 overflow period t0ov = 1/f0ov = 65.28ms
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default timer0 TOP: 78 (4Eh) -> timer period tp = 19.968ms
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1s interval: number of overflows nov1s = 1000ms/tp = 50.080128205 ≈ 50
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5min interval: nov5m = (1000ms*60*5)/tp = 15024.038461538 ≈ 15024
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24h interval: nov24h = 288*5min interval
definition of a significant temp change
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dT > 0.2°C
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everything else is not significant
detect phantom inner temp changes
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detection requires at least 2 controlling cycles
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inner temp changed for 0.5°C or more, while the outer temp did not change significant
dTi = significant && dTo <= 0.2°C
value tracking and processing
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on each controlling interval (every 5min) all temp values are processed by above controlling logic and are stored for at least one day
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in total we get 288 intervals: (60min*24h)/5min = 288 per day
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if there was no change on a 5min interval, within the current controlling cycle the previously captured temp values of the intervals are processed by above logic until either a change has been detected or all intervals are processed (up to one day)
parameter value overview
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time between cycle intervals: 5min
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mixer engine controlling time: 1s
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significant temp change: dT > 0.2°C
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detect phantom inner temp changes: dTi = significant && dTo <= 0.2°C
establishing UART conform serial communication (to receive temperature values)
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the reference document for this is: "doc4300.pdf", a kind of application note, renamed to "usi_hd_async.pdf"
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timer0 mode must be compare match A
to be clarified
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Disable USI -> how to explicitly do this? -> maybe by setting the clock source to none?